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01

Fresher Physical Design Engineer 

02

03

(Junior – Senior) Physical Design Engineer

(Junior – Senior) Design Verification Engineer

04

Foundry IP Engineer (CAD / Layout / Circuit Design)

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05

Intern Firmware

Benefits of Joining
FPT SEMICONDUCTOR

Work in a high-tech environment with a diverse ecosystem — from product design (ASIC, IP) to global projects.

Take part in exciting and challenging projects: AI chips, advanced process nodes, IP solutions, IoT devices, OSATs, and more.

Opportunity to become a full-time employee after successfully completing your internship at FSEMI.

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about FPT Semiconductor

FPT Semiconductor, a driving force in Vietnam's booming semiconductor industry, designs Power Management ICs and IoT ICs for a global market.

As a proud member of FPT Corporation, we are committed to cultivating lasting partnerships, fostering innovation, and contributing to the global technological ecosystem. With relentless dedication to quality and precision, our cutting-edge technology and talented team ensure that we stay at the forefront of the ever-evolving semiconductor landscape — delivering excellence to both domestic and international clients.

Thời gian làm việc Dự kiến
 Trong tháng 7
(Thời gian đào tạo, hướng dẫn: Tháng 6)

GIỚI THIỆU VỀ FPT IS

FPT IS là công ty cung cấp sản phẩm, giải pháp, dịch vụ chuyển đổi số hàng đầu tại Việt Nam và trong khu vực. Với 30 năm đồng hành cùng hơn 10.000 khách hàng là tổ chức, doanh nghiệp trên 25 quốc gia, FPT IS tin rằng công nghệ là đòn bẩy vững chắc để tổ chức, doanh nghiệp củng cố và gia tăng lợi thế cạnh tranh để phát triển bền vững. Tại FPT IS, chúng tôi không ngừng sáng tạo để giao dịch giữa chính phủ, doanh nghiệp và người dân diễn ra nhanh chóng, hiệu quả và tin cậy. Trong 5 năm tới, mỗi người dân và doanh nghiệp Việt Nam sẽ trải nghiệm ít nhất một sản phẩm, dịch vụ của FPT IS hàng ngày.
Sản phẩm
Made by FPT IS
70+
3,700+
Cán bộ nhân viên
25+
Quốc gia

Công ty Cổ phần Bán dẫn FPT

CẬP NHẬT THÔNG TIN

Email: info@fpt-semiconductor.com


https://fpt-semiconductor.com/vi/

Địa chỉ: FPT Tower, Số 10 Đường Phạm Văn Bạch, Phường Dịch Vọng, Quận Cầu Giấy, Hà Nội

Về đầu trang

©2025 FPT Semiconductor

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Physical Design Engineer (Fresher)

Danang Software Park No.2, Nhu Nguyet Street, Thuan Phuoc Ward, Hai Chau District, Danang City, Vietnam.

Responsibilities

- Participate in an on-the-job training program designed for fresh graduate, covering foundational to advanced skills. 
- Gain hands-on experience by contributing to real projects under the guidance of dynamic and supportive mentors.
- Take full PD flow from Netlist to GDS include floor-planning, placement, CTS, routing, STA and PV.

Requirements

- Finished a whole university course (recent graduation or waiting for receiving degree) in Electronic and Telecommunication, Computer Science, Electrical Engineering, Electronic Engineering or relevant.
- From 3.0/4.0 GPA.
- Have knowledge about Digital Design, Digital Processing, CMOS, Computer Architecture.
- A team player with a proactive attitude, a willingness to learn, and a positive mindset.
- Proficient in English, with a minimum score of 650 TOEIC, B2 CEFR, or 5.5 IELTS.
- Familiarity with Linux, Script python/tcl/csh.. are a plus.

Benefit & Perks

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:
- Working day: from Monday to Friday
- To be attended training courses to improve skill.
- Competitive salary in labor market
- “FPT care” health insurance provided by PIJICO and is exclusive for FPT employees
- Recharge and relax with paid annual summer vacation.
- 13th month salary
- Working in Danang, Viet Nam

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Design Verification Engineer
(Junior – Senior) 

Responsibilities

As an ASIC RTL Verification engineer, You will work closely with design team to review the design spec and define detailed testplan.
- Develop & maintain verification environment for module and SOC level using UVM methodology.
- Create and debug test cases, IP verification.
- Write and review verification plan.
- Use assertion based verification to verify module or SOC level.
- Perform code coverage analysis on module and SOC level.

Requirements

- Bachelor's or Master's degree in Electrical Engineering or Electronic Engineering.
- 2+ years experience in the area of digital IC verification. Candidates with more years of experience may be considered for Senior Engineer position.
- Working experience from design to tape-out are essential
Experience in system Verilog and UVM verification methodology
- Experience in using EDA tools from Cadence, Synopsys
- Knowledge and working experience in one or more of the following is a plus –
- Digital and DSP design
- Microprocessor / Graphics processor products
- Knowledge in connectivity technology such as USB, WIFI, Bluetooth, RFID, NFC, GPS, UART, SPI and I2C
- Embedded programming using C language

Nice to have:
- Good knowledge in digital design techniques and the state-of-the-art physical design methods.
- Solid fundamentals in IC design flow and ASIC concepts.

Benefit & Perks

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:
- Competitive salary in labor market
- Project bonuses when you join ODC (Offshore Development Center) projects
- 100% full salary in probation period
- "FPT care” health insurance provided by PIJICO and is exclusive for FPT employees
- Recharge and relax with paid annual summer vacation
- Opportunities to work onsite in Korea, Japan, or Taiwan
- Internal Training (Technical & Functional). Scope of English Training
- Working time: 8:30 AM-6:00 PM From Mondays to Fridays

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Foundry IP Engineer
(CAD/Circuit Design/Layout)

1. CAD DEVELOPER

Responsibilities
+ Use Python/TCL or C/C++ programing language to perform following task:
- Build and maintain compiling tool for GDS2 data used by Semiconductor IP design engineers
- Build up database structure for IC designing data and create tool to export data to corresponding output formats. 
- Build automation tools for data analysis and QA tool for design verification.
- Collaborate with Design team to understand the designing automation needs and build up support tools/scripts as request.
+ Participate in mentoring junior members.

Requirements
- Bachelor's or Master's degree in Software development, Computer science or relevant.
- 2Y+ of software development in Python or TCL programming language.
- Experience of Database design and Analysis.
- GUI design experience is a plus.
- Good background of IC logic gate (function, Logic Circuits, Boolean Algebra, and Truth Tables) and Hardware description languages such as Verilog/VHDL is a plus.
- Good English and communication skill.

2. CIRCUIT DESIGN ENGINEER

Responsibilities
- Design, implement, optimize, and verify customized analog and digital circuits to build up SRAM compilers for different design targets: High-speed, High-Density, and Low-Power.
- Collaborate with the Layout team for floor-planning and design optimization.
- Join with CAD team to develop and optimize the design and QA flow and in-house tools.
- Provide support in building silicon test chip and participate in design testing.
- Participate in mentoring junior members.

Requirements
- Bachelor's or Master's degree in Electrical Engineering, Electronic Engineering or relevant.
- 5Y+ years of SRAM designing. 
- Deep experience on SRAM designing and compiler implementation.
- Can technical lead design team while collaborate with layout and CAD team on design review, optimization, and QA to make sure all design qualities met. 
- Good background on QA flow and design methodology.
- Good English and communication skills.
- Management skill is a plus.

Benefit & Perks

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:
- Competitive salary in labor market
- Project bonuses when you join ODC (Offshore Development Center) projects
- 100% full salary in probation period
- "FPT care” health insurance provided by PIJICO and is exclusive for FPT employees
- Recharge and relax with paid annual summer vacation
- Opportunities to work onsite in Korea, Japan, or Taiwan
- Internal Training (Technical & Functional). Scope of English Training
- Working time: 8:30 AM-6:00 PM From Mondays to Fridays

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3. LAYOUT ENGINEER

Responsibilities
- Work with design team to build up SRAM design from spec.
- Participate in floorplanning and layout leafcell implementation.
- Handle layout verification (DRC/LVS/ERC/EMIR) on both leafcell level and top instance level.
- Setup and perform physical QA flow and Compiler integration for tape-out.
- Cooperate with design team on chip level integration of silicon testchip implementation.
- Participate in mentoring junior members.

Requirements
- Bachelor's or Master's degree in Electrical Engineering, Electronic Engineering or relevant.
- Good background of CMOS technology (behavior + characteristic) and logic gate (function, Logic Circuits, Boolean Algebra, and Truth Tables)
- 2Y+ in customized layout implementation. Experience in memory leafcell implementation, optimization, and verification. 
- Experience in memory layout floorplaning, power mesh planning, and key layout optimization.
- Good English and communication skills.

Intern Firmware

Diamond Tower, 63 Le Duc Tho, My Dinh, Ha Noi

Responsibilities

- Support firmware development for IoT and embedded tracking devices.
- Assist in writing, testing, and debugging C/C++ code on microcontrollers (e.g., STM32, ESP32).
- Conduct hardware testing, validation, and troubleshooting using lab equipment 
- Collaborate with the hardware and software teams to integrate and validate embedded systems.
- Work with communication protocols such as UART, SPI, I2C, BLE, and Wifi. 
Participate in prototype testing, field validation, and troubleshooting. 

Requirements

- Final-year student or recent graduate majoring in Electronics, Computer Engineering, Mechatronics, or a related field.
- Basic understanding of embedded systems, microcontrollers, and peripheral drivers.
- Familiar with C/C++ programming; Python is a plus.
- Assist in schematic design, PCB layout, and hardware prototyping for IoT and tracking devices 
Knowledge of common debugging tools (oscilloscope, logic analyzer, etc.).
- Good problem-solving mindset, eagerness to learn, and team spirit.
- Able to work at least 3 days/week on-site.

Benefit & Perks

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:
- Hands-on experience with real IoT products in a professional R&D environment.
- Mentorship from senior engineers in embedded systems and chip development.
- Exposure to the full product lifecycle: from design to deployment.
- Opportunity to receive a full-time offer based on your performance during the internship.

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Physical Design Engineer
(Junior – Senior) 

Responsibilities

As an ASIC Physical Design engineer, you will be responsible for all aspects of PnR, working with customer for technical related issue and input/output requirement, helping construct/modify design flow, physical verification, and timing closure.
- Responsible for 1 block or multiple blocks in the project from floorplan to tape-out.
- Responsible for physical verification, signal integrity, power integrity, timing closure.
- Develop and maintain methodology and flows related to PnR.
- Analyze reports and utilize scripting techniques to develop insights and drive rapid timing closure.
- Communicate with customers and others team for technical related issue and input/output requirement.

Requirements

- 1+ years of experience in ASIC physical design including floorplan, power planning, placement, clock tree synthesis, routing, timing, and signal integrity.
- Has knowledge of the full design cycle from RTL to GDSII, including chip level.
- Familiarity with all aspects of PnR of high-performance, mixed-signal SoCs in advanced process technology nodes (28nm and below).
- Experience on Synopsys or Cadence flow – ICC, Fusion, Innovus, PrimeTime, Formality, Calibre.
- Proficient in scripting languages (Shell, Tcl and Perl).
- Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups.
- Ability to build and lead teams, while providing training and mentorship to freshers, junior engineers, and mid-level engineers.

Nice to have:
- Good knowledge in digital design techniques and the state-of-the-art physical design methods.
- Solid fundamentals in IC design flow and ASIC concepts.

Benefit & Perks

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:
- Competitive salary in labor market
- Project bonuses when you join ODC (Offshore Development Center) projects
- 100% full salary in probation period
- "FPT care” health insurance provided by PIJICO and is exclusive for FPT employees
- Recharge and relax with paid annual summer vacation
- Opportunities to work onsite in Korea, Japan, or Taiwan
- Internal Training (Technical & Functional). Scope of English Training
- Working time: 8:30 AM-6:00 PM From Mondays to Fridays

APPLY NOW